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Design of Fully Integrated Programmable PLL Frequency Synthesizers for Microprocessor Clocking at 1-1500 MHz
刊名：
Russian Microelectronics
作者：
V. D. Baikov
A. A. Garmash
Yu. B. Rogatkin
A. N. Sevryukov
刊号：
736LB009
ISSN：
1063-7397
出版年：
2007
年卷期：
2007, vol.36, no.2
页码：
127-134
总页数：
8
分类号：
TN4
语种：
eng
文摘：
This paper is concerned with the design of fully integrated programmable PLL frequency synthesizers for microprocessor clocking at 1-1500 MHz. The focus is on the circuit configuration and performance parameters of the basic analog units of the PLL: the stabilized bias unit, phase-frequency detector, charge pump, loop filter, and voltage-controlled oscillator (VCO). The data examined are obtained by measurements on ICs fabricated by a 0.25- or 0.18-μm established CMOS technology. The circuit configurations are presented of VCOs that are tunable up to 1-1.3 GHz or up to over 2 GHz; they are designed to be implemented in a 0.25-or 0.18-μm technology, respectively. Also addressed is the design of the digital section of PLL synthesizers with a tuning range extending from 1 to over 1000 MHz. The PLL frequency and step responses, current consumption, and jitter performance are presented and investigated.
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